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FEATURES Dual Supply 5 V High-Speed Fully Buffered Inputs and Outputs 600 MHz Bandwidth (-3 dB) 200 mV p-p 500 MHz Bandwidth (-3 dB) 2 V p-p 1600 V/ s Slew Rate, G = +1 1350 V/ s Slew Rate, G = +2 Fast Settling Time: 4 ns Low Supply Current: <30 mA Excellent Video Specifications (RL = 150 ): Gain Flatness of 0.1 dB to 50 MHz 0.01% Differential Gain Error 0.01 Differential Phase Error "All Hostile" Crosstalk -80 dB @ 10 MHz -50 dB @ 100 MHz High "OFF" Isolation of 90 dB @ 10 MHz Low Cost Fast Output Disable Feature APPLICATIONS RGB Buffer in LCD and Plasma Displays RGB Driver Video Routers
500 MHz, G = +1 and +2 Triple Video Buffers with Disable AD8074/AD8075
FUNCTIONAL BLOCK DIAGRAM
AD8074 /AD8075
OE 1 DGND 2 IN2 3 AGND 4 IN1 5 AGND 6 IN0 7 VEE 8 G= +1/+2 G= +1/+2 G= +1/+2
16 VCC 15 VCC 14 OUT2 13 VEE 12 OUT1 11 VCC 10 OUT0 9 VEE
PRODUCT DESCRIPTION
Table I. Truth Table
The AD8074/AD8075 are high-speed triple video buffers with G = +1 and +2 respectively. They have a -3 dB full signal bandwidth in excess of 450 MHz, along with slew rates in excess of 1400 V/s. With better than -80 dB of all hostile crosstalk and 90 dB isolation, they are useful in many high-speed applications. The differential gain and differential phase error are 0.01% and 0.01. Gain flatness of 0.1 dB up to 50 MHz makes the AD8074/AD8075 ideal for RGB buffering or driving. They consume less than 30 mA on a 5 V supply. Both devices offer a high-speed disable feature that allows the outputs to be put into a high impedance state. This allows the building of larger input arrays while minimizing "OFF" channel output loading. The AD8074/AD8075 are offered in a 16-lead TSSOP package.
OE 0 1
OUT0, 1, 2 IN0, IN1, IN2 High Z
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
AD8074/AD8075-SPECIFICATIONS (T = 25 C, V =
A S
5 V, unless otherwise noted.)
Min 330/310 250/230 330/300 250/230 Typ 600/550 400/400 500/500 350/350 70/65 70/65 1600/1350 4/7.5 0.01 0.01 -80/-74 -50/-44 90 19.5/22 0.1/ 0.2 2.5 3 10 5 10 1.5 1.5 2.8/ 1.4 +VS - 1.95 -VS + 2.1 +VS - 2.35 -VS + 2.30 +VS - 1.8 -VS + 1.8 +VS - 2.2 -VS + 2.2 70 0.5 7.5 2.2 5.5 74 64 21.5/24 3/4 23/26 0.15/ 0.65 27/40 Max Unit MHz MHz MHz MHz MHz MHz V/s ns % Degrees dB dB dB nV/Hz % mV mV V/C A M pF pF V V V V V mA M pF V dB dB mA mA mA V V nA A C C/W C/W
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth (Small Signal) -3 dB Bandwidth (Large Signal) 0.1 dB Bandwidth Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Differential Gain Differential Phase All Hostile Crosstalk OFF Isolation Voltage Noise DC PERFORMANCE Voltage Gain Error Input Offset Voltage Input Offset Drift Input Bias Current INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Voltage Range OUTPUT CHARACTERISTICS Output Voltage Swing
Conditions VIN = 200 mV p-p, CL = 5 pF VIN = 200 mV p-p, RL = 150 VIN = 2 V p-p, CL = 5 pF VIN = 2 V p-p, RL = 150 VIN = 200 mV p-p, CL = 5 pF VIN = 200 mV p-p, RL = 150 2 V Step, RL = 1 k/150 2 V Step, RL = 1 k/150 V = 3.58 MHz, 150 V = 3.58 MHz, 150 V = 10 MHz, RL = 1 k V = 100 MHz, RL = 1 k V = 10 MHz, RL = 150 V = 10 kHz to 100 MHz No Load TMIN to TMAX
9.5/10
Channel Enabled Channel Disabled
RL = 1 k RL = 150
Short Circuit Current (Protected) Output Resistance Output Capacitance POWER SUPPLY Operating Range Power Supply Rejection Ratio Quiescent Current
Enabled Disabled Disabled
3.5
+PSRR: +VS = +4.5 V to +5.5 V, -VS = -5 V -PSRR: -VS = -4.5 V to -5.5 V, +VS = +5 V All Channels "ON" All Channels "OFF" TMIN to TMAX OE Input OE Input OE = 4 V OE = 0.4 V Operating (Still Air) Operating (Still Air) Operating
4.5 60 56
30 5.5
DIGITAL INPUT Logic "1" Voltage Logic "0" Voltage Logic "1" Input Current Logic "0" Input Current OPERATING TEMPERATURE RANGE Temperature Range JA JC
Specifications subject to change without notice.
2.0 0.8 100 1 -40 150.4 27.6 +85
-2-
REV. A
AD8074/AD8075
ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.0 V Internal Power Dissipation 2, 3 AD8074/AD8075 16-Lead TSSOP (RU) . . . . . . . . . . . . . 1 W Input Voltage IN0, IN1, IN2 . . . . . . . . . . . . . . . . . . . . . . . . . VEE VIN VCC OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND VIN VCC Output Short Circuit Duration . . . . . . . . . . . . . . . . . . Indefinite3 Storage Temperature Range . . . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . . . 300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air (T A = 25C). 3 16-lead plastic TSSOP; JA = 150.4C/W. Maximum internal power dissipation (P D) should be derated for ambient temperature (T A ) such that PD < (150C - T A)/JA.
ORDERING GUIDE
Model AD8074ARU AD8075ARU AD8074-EVAL AD8075-EVAL Temperature Range -40C to +85C -40C to +85C Package Description 16-Lead Plastic TSSOP 16-Lead Plastic TSSOP Evaluation Board Evaluation Board Package Option RU-16 RU-16
PIN CONFIGURATION
AD8074 /AD8075
OE 1 DGND 2 IN2 3 AGND 4 IN1 5 AGND 6 IN0 7 VEE 8 G= +1/+2 G= +1/+2 G= +1/+2
16 VCC 15 VCC 14 OUT2 13 VEE 12 OUT1 11 VCC 10 OUT0 9 VEE
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8074/AD8075 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
MAXIMUM POWER DISSIPATION
MAXIMUM POWER DISSIPATION - Watts
1.5 TJ = 150 C
The maximum power that can be safely dissipated by the AD8074/ AD8075 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175C for an extended period can result in device failure. While the AD8074/AD8075 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves shown in Figure 1.
1.0
0.5
0 -50
-30
-10
0
10
30
50
70
90
AMBIENT TEMPERATURE - C
Figure 1. Maximum Power Dissipation vs. Temperature
REV. A
-3-
AD8074/AD8075-Typical Performance Characteristics
1 GAIN 0 -1 -2 FLATNESS 200mV p-p 0.3 0.2 0.1 0.4
1 0 -1 NORMALIZED GAIN - dB -2 -3 -4 -5 -6 2V p-p -7 -8 -9 0.1 FLATNESS 200mV p-p
FLATNESS - dB
0.4 GAIN 0.3 2V p-p NORMALIZED FLATNESS - dB NORMALIZED FLATNESS - dB 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 1000
GAIN - dB
-3 -4 -5 -6 -7 -8 -9 0.1 2V p-p
0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 1000
1
10 FREQUENCY - MHz
100
1
10 FREQUENCY - MHz
100
TPC 1. AD8074 Frequency Response; RL = 150
TPC 4. AD8075 Frequency Response; RL = 150
2 1 0 -1 -2 GAIN
0.6 0.5 0.4
2 1 0 NORMALIZED GAIN - dB -1 2V p-p -2 -3 -4 -5 -6 -7 -8 -9 -10 0.1 1 10 100 FREQUENCY - MHz 200mV p-p FLATNESS 2V p-p GAIN
0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 1000
0.3 2V p-p FLATNESS
-3 -4 -5 -6 -7 -8 -9 200mV p-p 2V p-p
0.1 0 -0.1 -0.2
200mV p-p
-0.3 -0.4 -0.5
-10 0.1
1
10 FREQUENCY - MHz
100
-0.6 1000
TPC 2. AD8074 Frequency Response; RL = 1 k, CL = 5 pF
FLATNESS - dB
0.2
GAIN - dB
TPC 5. AD8075 Frequency Response; RL = 1 k, CL = 5 pF
3 2 1 CL = 10pF
3 2 1
NORMALIZED GAIN - dB
CL = 10pF
0 -1 CL = 0pF CL = 5pF
0 -1 -2 -3 -4 -5 -6 -7 -8 VIN 75 CL VOUT 150k CL = 0pF CL = 5pF
GAIN - dB
-2 -3 -4 -5 -6 -7 -8 -9 VOUT = 2V p-p 1 VIN 75 CL
VOUT 1k
-9
10 FREQUENCY - MHz 100 1000
VOUT = 2V p-p 1 10 FREQUENCY - MHz 100 1000
-10 0.1
-10 0.1
TPC 3. AD8074 Frequency Response vs. Capacitive Load
TPC 6. AD8075 Frequency Response vs. Capacitive Load
-4-
REV. A
AD8074/AD8075
0 -10 -20 -30
CROSSTALK - dB CROSSTALK - dB
0 VOUT = 2V p-p (ACTIVE CHANNEL(s)) RL = 1k RT = 37.5 -10 -20 -30 -40 -50 -60 -70 -80 ADJACENT ADJACENT -90 -100 -110 0.1 1 10 FREQUENCY - MHz 100 1000 0.1 1 10 FREQUENCY - MHz 100 1000 ALL-HOSTILE VOUT = 2V p-p (ACTIVE CHANNEL(s)) RL = 150 RT = 37.5
-40 -50 -60 -70 -80 -90 -100 -110 ALL-HOSTILE
TPC 7. AD8074 Crosstalk vs. Frequency (All Hostile and Adjacent RL = 1 k)
TPC 9. AD8075 Crosstalk vs. Frequency (All Hostile and Adjacent RL = 150 )
0 -10 -20
DISTORTION - dBc
0
VOUT = 2V p-p RL = 150 RT = 37.5
-10 -20
DISTORTION - dBc
VOUT = 2V p-p RL = 150 RT = 37.5
-30 -40 -50 -60 -70 -80 -90 -100 1 10 100 1000 FUNDAMENTAL FREQUENCY - MHz THIRD HARMONIC SECOND HARMONIC
-30 -40 -50 -60 -70 -80 -90 -100 1 10 100 1000 FUNDAMENTAL FREQUENCY - MHz THIRD HARMONIC SECOND HARMONIC
TPC 8. AD8074 Distortion vs. Frequency
TPC 10. AD8075 Distortion vs. Frequency
REV. A
-5-
AD8074/AD8075
-20 -30 -40
OFF ISOLATION - dB
-20 -30 -40
-50 -60 -70 -80 -90 -100 -110 0.1 1 10 FREQUENCY - MHz 100 1000 RL = 150 RL = 1k
OFF ISOLATION - dB
-50 -60 -70 -80 -90 -100 -110 0.1 1 10 FREQUENCY - MHz 100 1000 RL = 150 RL = 1k
TPC 11. AD8074 Off Isolation vs. Frequency
TPC 14. AD8075 Off Isolation vs. Frequency
10 0 -10 -20
PSRR - dB
20 10 0
-PSRR PSRR - dB
-10 +PSRR -20 -PSRR -30 -40 -50 -60 -70
-30 +PSRR -40 -50 -60 -70 -80 0.1 1 10 FREQUENCY - MHz 100 1000
0.1
1
10 FREQUENCY - MHz
100
1000
TPC 12. AD8074 PSRR vs. Frequency
TPC 15. AD8075 PSRR vs. Frequency
350 300
400 350
VOLTAGE NOISE - nV/ Hz
VOLTAGE NOISE - nV/ Hz
250 200 150 100 50 0
300 250 200 150 100 50 0 10
10
100
1k 10k FREQUENCY - Hz
100k
1M
100
1k 10k FREQUENCY - Hz
100k
1M
TPC 13. AD8074 Voltage Noise vs. Frequency
TPC 16. AD8075 Voltage Noise vs. Frequency
-6-
REV. A
AD8074/AD8075
10000
10000
1000
INPUT IMPEDANCE - k
1000
100
INPUT IMPEDANCE - k
0.1 1 10 FREQUENCY - MHz 100 1000
100
10
10
1
1
0.1
0.1
0.01
0.01 0.1 1 10 FREQUENCY - MHz 100 1000
TPC 17. AD8074 Input Impedance vs. Frequency
TPC 20. AD8075 Input Impedance vs. Frequency
1000
1000
100
OUTPUT IMPEDANCE -
OUTPUT IMPEDANCE -
100
10
10
1
1
0.1 0.1 1 10 FREQUENCY - MHz 100 1000
0.1 0.1 1 10 FREQUENCY - MHz 100 1000
TPC 18. AD8074 Output Impedance vs. Frequency; Enabled
TPC 21. AD8075 Output Impedance vs. Frequency; Enabled
1000
1000
100
100
OUTPUT IMPEDANCE - k
OUTPUT IMPEDANCE - k
10
10
1
1
0.1
0.1
0.01
0.01
0.001 0.1 1 10 FREQUENCY - MHz 100 1000
0.001 0.1 1 10 FREQUENCY - MHz 100 1000
TPC 19. AD8074 Output Impedance vs. Frequency; Disabled
TPC 22. AD8075 Output Impedance vs. Frequency; Disabled
REV. A
-7-
AD8074/AD8075
0.15 VO = 200mV STEP 0.10
0.15 VO = 200mV STEP 0.10
0.05
0.05
0
0
-0.05
-0.05
-0.10 2ns -0.15
-0.10 2ns -0.15
TPC 23. AD8074 Small Signal Pulse Response (RL = 1 k, CL = 5 pF)
0.8 0.7 0.6 0.5 0.4 VO = 700mV STEP
TPC 26. AD8075 Small Signal Pulse Response (RL = 150 k)
0.8 0.7 0.6 0.5 0.4 VO = 700mV STEP
0.3
0.3
0.2
0.2
0.1 0 2ns -0.1 -0.2
0.1 0 2ns -0.1
TPC 24. AD8074 Video Amplitude Pulse Response (RL = 1 k, CL = 5 pF)
TPC 27. AD8075 Video Amplitude Pulse Response (RL = 150 )
1.5 VO = 2V STEP 1.0
1.5 VO = 2V STEP 1.0
0.5
0.5
0
0
-0.5
-0.5
-1.0 2ns -1.5
-1.0 2ns -1.5
TPC 25. AD8074 Large Signal Pulse Response (RL = 1 k, CL = 5 pF)
TPC 28. AD8075 Large Signal Pulse Response (RL = 150 )
-8-
REV. A
AD8074/AD8075
THEORY OF OPERATION
The AD8074 (G = +1) and AD8075 (G = +2) are triple-channel, high-speed buffers with TTL-compatible output enable control. Optimized for buffering RGB (red, green, blue) video sources, the devices have high peak slew rates, maintaining their bandwidth for large signals. Additionally, the buffers are compensated for high phase margin, minimizing overshoot for good pixel resolution. The buffers also have video specifications that are suitable for buffering NTSC or PAL composite signals. The buffers are organized as three independent channels, each with an input transconductance stage and an output transimpedance stage. Each channel is characterized by low input capacitance and high input impedance. The transconductance stages, NPN differential pairs, source signal current into the folded cascode output stages. Each output stage contains a compensating network and emitter follower output buffer. Internal voltage feedback sets the gain, the AD8074 being configured as a unity gain follower, and the AD8075 as a gain-of-two amplifier with a feedback network. The architecture provides drive for a reverseterminated video load (150 ) with low differential gain and phase error for relatively low power consumption. Careful chip design and layout allow excellent crosstalk isolation between channels. One logic pin, OE, controls whether the three outputs are enabled, or disabled to a high-impedance state. The high impedance disable allows larger matrices to be built when busing the outputs together. When disabled, the AD8074 and AD8075 consume a fifth the power as when enabled. In the case of the AD8075 (G = +2), a feedback isolation scheme is used so that the impedance of the gain-of-two feedback network does not load the output. Full power bandwidth for an undistorted sinusoid is often calculated using peak slew rate from the equation:
APPLICATIONS Response Tuning
It has been mentioned in passing that the primary cause of overshoot for the AD8074 and AD8075 is the presence of large reactive loads at the output. If the system exhibits excessive ringing while settling, a 10 -50 series resistor may be used at the output to isolate the emitter-follower output buffer from the reactive load. If the output exhibits an overdamped response, the system designer may add a few pF shunt capacitance at the output to tune for a faster edge transition. A system with a small degree of overshoot will settle faster than an overdamped system.
2.0 1.5 1.0 0.5 0 -0.5 -1.0 VIN -1.5 -2.0 75 RS CL 1k 2ns RS = 20 CL = 15pF RS = 0 CL = 5pF RS = 10 CL = 10pF
VOUT
Figure 2. Driving Capacitive Loads
Single Supply Operation
The AD8074 and AD8075 may be operated from a single 10 V supply. In this configuration, the AD8075's AGND pins must be tied near midsupply, as AGND provides the reference for the ground buffer, to which the internal gain network is terminated. Logic is referenced to DGND. The buffers are disabled in single supply operation for VOE > V DGND + ~2.0 V and enabled for VOE < VDGND + 0.8 V. TTL logic levels are expected. The following restrictions are placed upon the digital ground potential:
3.5 V VAVCC - VDGND 12 V VDGND VAVEE
Full Power Bandwidth =
Peak Slew Rate 2 x x Sinusoidal Amplitude
Peak slew rate is not the same as average slew rate (25% to 75%) which is typically specified. For a natural response, peak slew rate may be 2.7 times larger than average slew rate. Therefore, calculating a full power bandwidth with a specified average slew rate will give a pessimistic result. The primary cause of overshoot in these amplifiers is the presence of large reactive loads at the output and insufficient series isolation of the load. However, it is possible to overdrive these amplifiers with 1 V, subnanosecond input-pulse edges. The ensuing dynamics may give rise to subnanosecond overshoot. To reduce these effects, an edge-rate limiting network at the input should be considered for input transition times less than 0.5 ns.
The architecture of the output buffer is such that the output voltage can swing to within ~2.3 V of either rail. For example, if the output need swing only 2 V, then the buffers could be operated on dual 3.5 V or single 7 V supplies. It is cautioned that saturation effects may become noticeable when the output swings within 2.6 V of either rail. The system designer may opt to use this characteristic to his or her advantage by using the soft-saturation regime, (2.2 V-2.6 V from the supply rails), to tame excessive overshoot. The designer is cautioned that a charge storage associated time delay of several nanoseconds is incurred when recovering from soft-saturation. This effect results in longer settling tails.
REV. A
-9-
AD8074/AD8075
RGB Buffer for Second Monitor
The RGB signals for PC monitors are driven through coax cables whose characteristic impedance is 75 . The graphics chip will generally have current-source output drivers that should be double terminated with a 75 shunt termination at each end. On the transmit end, the shunt terminations are provided to ground close to the graphics IC, while the monitor terminates its end via internal termination resistors. While this scheme works well and is virtually foolproof for a single monitor, it leaves no means for passively connecting a second monitor to the same source. A second monitor that is connected simply in parallel will provide an extra set of terminations that will upset the signal levels. To keep costs low, most computer monitors do not have the ability to open-circuit the terminations in order that an additional monitor
can be connected to the same signal, as is done in some studiotype TV monitors. A way around this problem is to connect the first monitor to the RGB channels in the standard fashion, and then to provide a triple gain-of-two buffer to drive the second monitor. The AD8075 is designed to provide this function and also provide excellent high-frequency performance for high-resolution graphics signals. Figure 3 shows a schematic of this circuit. The outputs of the AD8075 are low impedance voltage sources and are therefore series-terminated with 75 resistors. The internal resistors in Monitor #2 provide the terminations at its end. The overall effect of this type of termination scheme is to divide the signal amplitude by two. This is compensated by the gain of two provided by the AD8075.
PC GRAPHICS IC R 75 75
MONITOR #1
CURRENT SOURCE OUTPUT DRIVERS
G 75 75
INTERNAL TERMINATIONS
B 75 75
+5V
+5V
+5V
25 F
+
0.1 F
0.1 F
0.1 F
MONITOR #2
75 75
AD8075
75 75 INTERNAL TERMINATIONS
75 75
25 F
+
0.1 F
0.1 F
0.1 F
-5V
-5V
-5V
Figure 3. Buffer
-10-
REV. A
AD8074/AD8075
Triple Video Multiplexer
The AD8074 and AD8075 each have an output-enable function that can be used to disable the outputs and put them in a highimpedance state. Usually, for a unity-gain device, it is relatively easy to provide high disabled impedance, because the feedback path is from the output to a high-impedance input. However, for a non-unity-gain part, the feedback provides a resistive path to ground. This will usually dominate the disabled output impedance, and make it a much lower value than the unity-gain device. The AD8075 has an internal buffer that provides a low-impedance, ground level output that terminates the feedback path during enabled operation. In the disabled state, both this buffer output
+5V +5V
and the amplifier output are disabled to a high impedance to provide a high-impedance disabled state. To construct a multiplexer, the outputs from one or more devices are connected in parallel and only one device is enabled at a time while all of the others are disabled. The two sets of inputs are applied individually to each of the separate device inputs. Figure 4 shows the circuit details for this function. The first RGB Source 1 is input to the first AD8075. Each of the individual signals is terminated to ground with 75 to provide proper termination for the input cables. In a similar fashion, the Source 2 signals are input to the second AD8075.
+5V
25 F
+
0.1 F
0.1 F
0.1 F
75 R 75 R
AD8075
75 SOURCE 1 G 75 G OUTPUT
75 B 75 OE B
25 F
+
0.1 F
0.1 F
0.1 F
-5V
-5V
-5V
SEL1/SEL2 +5V +5V +5V
25 F
+
0.1 F
0.1 F
0.1 F
OE 75 R 75
AD8075
75 SOURCE 2 G 75
75 B 75
25 F
+
0.1 F
0.1 F
0.1 F
-5V
-5V
-5V
Figure 4. Mux
REV. A
-11-
AD8074/AD8075
Each of the six outputs has a 75 series resistor that is used to reverse-terminate the output transmission line. The corresponding outputs are then wired in parallel and delivered to the output cable. The termination resistors in this position help to isolate the off capacitance of the disabled device's outputs from loading the enabled device's outputs. The gain-of-two of the AD8075 compensates for the signal halving that occurs as a result of the output terminations. A select signal is provided directly to the OE of the second AD8075 and an inverted version is used to drive the other device's OE. This will ensure that only one device is active at a time. Since there is a total of 150 in series between any two outputs, it is not essential to be overly concerned about the exact timing of the making and breaking of the enable signals. Additional inputs can easily be added to the circuit shown to make wider multiplexers. The outputs of all of the devices will be wired in parallel, and the logic must allow that only one output be enabled at a time. If it is desired to make a triple 3:1 multiplexer, a triple 2:1 multiplexer, like the AD8185 can be used along with the AD8075. The same general guidelines for input and output treatment should be followed and the logic must perform the proper function. If it is desired to design such a multiplexer at unity gain, the AD8074 should be used. For a triple 3:1 multiplexer, an AD8183 (triple 2:1 mux) can be combined with an AD8074 to provide this function.
Layout and Grounding
A major area of focus should be the power distribution system. There should be a full ground plane that provides the reference and return paths for both the inputs and outputs. The ground also provides isolation between the input signals to minimize the crosstalk. This ground plane should cover as wide an area as possible and be minimally interrupted in order to keep its impedance to a minimum. The power planes should also be as broad as possible to provide minimal inductance, which is required for high-slew-rate signals. These power planes layers should be spaced closely to the ground plane to increase the interplane capacitance between the supplies and ground. Each supply pin should be bypassed with a low inductance 0.1 F ceramic capacitance with minimal excess circuit length to minimize the series impedance. A 25 F tantalum electrolytic capacitor will supply a charge reservoir for lower frequency, high-amplitude transitions. The input and output signals should be run as directly as possible in order to minimize the effects of parasitics. If they must run over a longer distance of more than a few centimeters, controlled impedance PCB traces should be used to minimize the effect of reflections due to mismatches in impedance and the proper termination should be provided. To avoid excess crosstalk, the above recommendations should be followed carefully. The power system and signal routing are the most important aspects of preventing excess crosstalk. Beyond these techniques, shielding can be provided by ground traces between adjacent signals, especially those that travel parallel over long distances.
The AD8074 and AD8075 are extreme bandwidth, high-slew-rate devices that are designed to drive up to the highest resolution monitors and provide excellent resolution. To realize their full performance potential, it is essential to adhere to the best practices of high-speed PCB layout.
-12-
REV. A
AD8074/AD8075
TP2 VEE P1 1 VEE DO NOT INSTALL VEE IMPEDANCE LINE
+
C2 10 F
50
AGND VCC R16 20k W2 VCC TP5 DISOUT DISOUT 50 AGND IMPEDANCE LINE AGND R11 50 DO NOT INSTALL AGND IN2 IN2 75 IMPEDANCE LINE DO NOT INSTALL R1 75 AGND IN1 IN1 75 IMPEDANCE LINE AGND AGND AGND 75 IMPEDANCE LINE VEE R3 75 AGND C6 0.1 F AGND C8 0.01 F AGND 1 OE 2 DGND 3 IN2 4 AGND 5 IN1 6 AGND 7 IN0 8 VEE VCC 16 VCC 15 OUT2 14 VEE 13 OUT1 12 VCC 11 OUT0 10 VEE 9 C11 0.01 F AGND VEE VCC C12 0.01 F AGND AGND DUT C7 0.1 F C3 0.1 F C15 0.01 F AGND P1 3 AGND P1 2 TP1 VCC AGND AGND
TP3
TP4
AGND DO NOT INSTALL VCC IMPEDANCE LINE
AGND
+
C1 10 F
50
VCC C14 0.01 F
AGND R7 75 VEE C13 0.01 F AGND R8 75
75
IMPEDANCE LINE OUT2
OUT2
R6 150 DO NOT INSTALL AGND
AGND
R2 75 AGND IN0 IN0
75
IMPEDANCE LINE OUT1
OUT1
R10 150 DO NOT INSTALL AGND AGND
AD8074
R9 75
75
IMPEDANCE LINE OUT0
OUT0
R12 150 DO NOT INSTALL AGND AGND
Figure 5. Evaluation Board Schematic
REV. A
-13-
AD8074/AD8075
Figure 6. Component Side
Figure 8. Silkscreen Top
Figure 7. Circuit Side
Figure 9. Silkscreen Bottom
Figure 10. Internal 2
-14-
REV. A
AD8074/AD8075
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm). Controlling Dimension: Metric, shown in parentheses.
16-Lead TSSOP (RU-16)
0.201 (5.10) 0.193 (4.90)
16
9
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
1 8
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
SEATING PLANE
0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
8 0
0.028 (0.70) 0.020 (0.50)
REV. A
-15-
AD8074/AD8075 Revision History
Location Data Sheet changed from REV. 0 to REV. A. Page
Addition to equation in SINGLE SUPPLY OPERATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
C02391-0-10/01(A)
-16-
REV. A
PRINTED IN U.S.A.

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